1. Field of the Invention
The present invention generally relates to the field of circuit modeling, and more specifically, to gate delay models.
2. Description of the Relevant Art
To shorten design cycles, digital systems are often designed at a gate and/or cell level. In contrast to designing at a transistor level, gate or cell level design can significantly reduce costly design verification by precharacterizing gate and cell delays for static timing analysis. The cell delays and transitions are generally expressed empirically as a function of load capacitance and input signal transition time. However, with the emerging interconnect dominance, gate loads can no longer be modeled by purely capacitive loads for high performance digital circuits.
For digital IC technologies in general, and CMOS in particular, it is assumed that a load at an output of the gate has a negligible impact on the waveform behavior at a gate input. Therefore, digital circuit delay calculation along timing paths can be performed gate by gate or logic state by logic state for applications such as timing analysis. It should be noted that the gate-source and gate-drain capacitances are included as part of the gate characterization and, therefore, not considered during the partitioning process.
Delay calculation is performed for each logic gate/state input individually. It is assumed that all other gate inputs are set to logic values such that an input pin under consideration can cause a gate output to transition. The outputs that are expected from a delay calculator are the waveforms at the fan-outs, as a function of the waveform at the switching input pin.
There are two approaches to gate delay modeling, which have gained widespread acceptance. The first is empirically derived expressions or look-up tables for delay and output-signal transition as a function of load capacitance and input-signal transition time (k-factor equations), which is further described below. The second is a switch-resistor model comprised of a linear resistor and a step function of voltage, also described below. Both methods are empirically based, since even the second method requires empirical fitting to approximate the resistance value.
Switch resistor models have an advantage that their coupling with an RC interconnect is inherently modeled. That is, the resistance model is able to capture the interaction of the gate's output resistance and the RC load. Timing analysis tools such as TV and Crystal were developed using switch-resistor models to analyze the transistor level circuit descriptions. The main difficulty with these approaches is calculating a single linear resistor, which captures the switching behavior of a CMOS gate. Recognizing that this resistance is a function of the gate's input signal transition. Recognizing that this resistance is a function of the gate's input signal transition time and output load, in a single output resistance for the gate is empirically derived. That is, the resistance is calculated as the average output impedance over a range of input signal transition times and output loads.
When the load is purely capacitive, one can completely precharacterize a gate's delay and output signal behavior as a function of input signal transition time, ttr-in, and load capacitance, CL. The experimental data for delay, td, and gate-output waveform transition time, ttr-out, are generally fitted to k-factor equations:td=k(ttr-in′CL)ttr-out=k′(ttr-in′CL)where k and k′ are empirically fitted functions, and the delay and transition times are defined as shown in FIG. 1. Note that the waveforms are simplified as saturated ramps by fitting a line through two predefined characterization points. With this approximation it is possible to represent the waveshape with a single number, the transition time.
Some methodologies use more than two points to characterize the waveshape, while others employ more complex load models—both of which increase the complexity of delay calculation significantly. These types of characterizations are mainly used for back-end verification processes for which speed is not critically important.
The delay and output transition time can also be characterized via look-up tables. The construction of such a table is illustrated in FIG. 2. Generally, gate delays may be characterized with look-up tables, they may be equally applicable to k-factor delay models (regression fit of table data) as well.
Due to the increase in total metal resistance with scaling, and the tendency for the effective gate output resistances to decrease as technologies are advanced, the RC shielding effect becomes significant for deep submicron CMOS. To illustrate this point, consider a simple gate model driving a distributed RC interconnect, with a load capacitance at the end of the line, as shown in FIG. 3. Assume that a resistance and a Thevenin voltage source that are functions of input transition time and output capacitance load model the gate. In this case, assume that the gate output resistance, Rd, and Thevenin voltage signal were selected as those values that would yield the same output delay and transition time as the actual gate when the load is the total capacitance, CM+CL.
If Rd>>RM, then the gate delay is accurately characterized by the empirical model as a function of total capacitance. However, if one considers the same gate resistance and total load capacitance, but increases the metal resistance so that Rd<<RM, the gate delay at node vout will decrease. This decrease in delay is due to the metal resistance shielding a portion of the downstream load capacitance. The difference in responses is sketched in FIG. 3. Note that the gate delay decreases, but the overall delay at CL would increase due to an increase in RM. In addition, the responses for lines with significant metal resistance also tend to have non-digital shaped waveforms as shown.
In order to preserve the simplicity and efficiency of the empirical gate models for complex RC loads, one can map the complex load to an effective capacitance (Ceff). Since its invention, the Ceff approach has been successfully used in the design of high-speed ICs.
The simplest model of a gate and corresponding interconnect delay would be a two-step approximation, in which a complete stage delay is the sum of the gate and interconnect delays. To capture the gate delay using a simple empirical gate delay model, the RC load is replaced by the effective capacitance, Ceff, and then the gate delay and output transition time is obtained from the empirical model of the gate. Once the transition time at the gate output is calculated, the gate output wave-form is approximated with a saturated ramp. The interconnect delay is then calculated using this saturated ramp waveform as the input excitation. This two-step delay approximation works well when the load seen by the gate is accurately approximated by the total capacitance of the net. That is, if the metal resistance is negligible, the whole interconnect behaves like an equi-potential surface and the waveform at the gate output appears instantly at all fan-outs—i.e., there is no slope degradation or delay from gate output to fan-outs.
However, with increasing effects of interconnect resistance, gate output waveforms become increasingly non-digital and can no longer be modeled as saturated ramps. A conventional response to this problem is to use Thevenin gate models based on the Ceff concept. As shown in FIG. 4, a time-varying voltage source and a constant resistor replaces the gate. Based on a gate input wave-form, A, the gate is modeled as a linear Thevenin equivalent with a time-varying voltage waveform, T. The voltage waveshape T is iteratively determined as a function of the effective capacitance. Once the Thevenin model is parameterized, the interconnect is then attached to the linear gate model and a linear circuit evaluation is performed. With this modeling approach, the RC nature of the interconnect can be captured to obtain the gate output and fan-out waveforms more accurately.
The Thevenin voltage waveform T is generally modeled via a saturated ramp voltage that is characterized by a transition time Δt and a delay t0. The values of the Thevenin model parameters, t0, Δt, and Rd, are chosen such that the waveshape at the model output and the actual waveform from the library lookup match. However, since the look-up tables and k-factor equations are not defined for noncapacitive loads we need to use an intermediate effective capacitance value, Ceff. To find Ceff, a commonly used procedure is to compute a capacitance value such that when the driver is the Thevenin model, the average current into the interconnect and Ceff are equal. Once Ceff is computed, it is used in the library lookup to obtain the gate output (delay and transition time). Then a Thevenin voltage is computed to match the library response.
A problem with conventional approaches, including the Thevenin equivalent model, is that they fail to represent the real physics or transistors, and hence, the calculations provide less than desired accuracy in gate modeling. In addition, in models such as Thevenin equivalents, only resistance is accounted for while in actuality, there is also capacitance present at the gate that does not get accounted. Again, this leads to less than desired accuracy in gate modeling. Yet another problem is that the actual circuit resistance is nonlinear although conventional modeling show resistance as linear, which also leads to further inaccuracies in gate modeling.
Therefore, there is a need for a system and process to provide more accurate gate modeling for use in circuit models and designs.